The Intel® E7500 chipset, a volume chipset, supports dual-processor (DP) server systems optimized for the Intel® Xeon® processor with 512 KB L2 cache and Intel® NetBurst® microarchitecture. The Intel E7500 chipset design delivers maximized system bus, memory and I/O bandwidth to enhance performance, scalability and end-user productivity while providing a smooth transition to next-generation server technologies.
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|Supports 2 Intel® Xeon® processors with 512 KB L2 cache for dual-processing server systems||Delivers a platform that brings Intel NetBurst® microarchitecture and the Intel® Hyper-Threading Technology of the Intel® Xeon® processor to deliver best-in-class performance for peak server workloads.|
|400 MHz system bus capability||Supports a high-performance, balanced platform by enabling a 3.2 GB/s system bus bandwidth that can support greater memory and I/O bandwidths.|
|Intel® Hub Architecture 2.0 connection to the MCH||This point-to-point connection between the MCH and the 3 P64H2 devices provides greater than 1 GB/s of bandwidth. Error Code Correction (ECC) protection, coupled with high data transfer rates, support I/O segments with greater reliability and faster access to high-speed networks.|
|64-bit PCI/PCI-X Controller Hub-2||Introduces next-generation PCI/PCI-X performance and significantly enhances platform flexibility. Two independent 64-bit, 133 MHz PCI-X segments and 2 hot-plug controllers (1 per segment) for each P64H2 allow up to 6 PCI-X buses per system.|
|Dual-channel DDR-200 memory interface||Offers a maximum memory bandwidth of 3.2 GB/s through a 144-bit wide, 200 MHz Double Data Rate (DDR) SDRAM memory interface with densities up to 512 megabits.|
|Advanced platform RASUM||Provides a more reliable platform with features such as memory Error Correction Code (ECC) with Intel® x4 Single Device Data Correction (Intel® x4 SDDC), hardware memory scrubbing, MCH SMBus target interface, hub interface ECC, and the availability of enhanced error status information maintained through reset.|
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|1005 Flip Chip-Ball Grid Array (FC-BGA)|
82801CA Integrated Controller Hub (ICH3-S)
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|421 Ball Grid Array (BGA)|
Intel® 82801CA I/O Controller Hub 3 (ICH3-S) Specification Update
82870P2 64-bit PCI/PCI-X controller (P64H2)
File Type/Size: PDF 1610KB
|567 Flip Chip-Ball Grid Array (FC-BGA)|
Requires an Intel® Hyper-Threading Technology (Intel® HT Technology)-enabled system, check with your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on the Intel® Core™ i5-750. For more information, including details on which processors support HT technology, visit www.intel.com/content/www/us/en/architecture-and-technology/hyper-threading/hyper-threading-technology.html.
In a x4 DDR memory device, the Intel® x4 Single Device Data Correction (Intel® x4 SDDC), provides error detection and correction for 1, 2, 3, or 4 data bits within that single device and provides error detection, up to 8 data bits, within two devices.